|Title||Frequency and time domain characterization of substrate coupling effects in 3D integration stack|
|Publication Type||Conference Paper|
|Year of Publication||2010|
|Authors||Eid E, Lacrevaz T., Bermond C., Capraro S., Roullard J., Fléchet B., Cadix L., Farcy A., Ancey P., Calmon F., Valorge O., Leduc P.|
|Conference Name||Electronic Manufacturing Technology Symposium (IEMT), 2010 34th IEEE/CPMT International|
|Keywords||3D integration stack, Couplings, Dielectrics, Electrodes, electromagnetic interference, frequency characterization, Frequency measurement, integrated circuit interconnections, Radio frequency, redistribution layers, stacked silicon substrates, substrate coupling effects, Substrates, three-dimensional integrated circuits, through silicon vias, Through-silicon vias, time domain characterization|
In new circuits performed with 3D integration technology, electromagnetic interference through stacked silicon substrates may occur due to signals propagated in Through Silicon Vias (TSV) and along Redistribution Layers (RDL). So, to optimize electrical performances of these new 3D digital or RF circuits, substrate coupling effects need to be characterized, modeled and quantified in a large frequency bandwidth. In this paper, we mainly analyze substrate coupling effects using dedicated capacitive test structures These structures are characterized using aggressive RF or high speed signals propagated along Through Silicon Vias (TSV). These RF or time domain signals in TSV are used to generate parasitic noise signals in silicon substrates. By analyzing the extracted results, solutions will be proposed to reduce this substrate noise.