|Title||Characterization and modeling of RF substrate coupling effects due to vertical interconnects in 3D integrated circuit stacking|
|Publication Type||Conference Paper|
|Year of Publication||2010|
|Authors||Eid E, Lacrevaz T., Bermond C., De Rivaz S., Capraro S., Roullard J., Cadix L., Fléchet B., Farcy A., Ancey P., Calmon F., Valorge O., Leduc P.|
|Conference Name||Signal Propagation on Interconnects (SPI), 2010 IEEE 14th Workshop on|
|Keywords||3D integrated circuit stacking, Circuit optimization, Coupling circuits, electrical models, integrated circuit interconnections, Integrated circuit modeling, Predictive models, Radio frequency, radio frequency characterizations, radiofrequency integrated circuits, radiofrequency measurement, RF measurements, RF substrate coupling effects, Silicon, Stacking, substrate coupling, three-dimensional integrated circuits, through silicon vias interconnects, Through-silicon vias, vertical interconnects|
This paper discusses substrate coupling effects in 3D integrated circuits carried by TSV interconnects (Through Silicon Vias). These electrical couplings lead to several impacts on 3D circuit performance. RF (Radio Frequency) characterizations have been performed on dedicated test structures in order to extract electrical models of substrate coupling and make obvious this phenomenon. New modeling tools for predictive studies have been validated thanks to a good compatibility between RF measurements and RF models.